Integrated circuits, or ICs, are created by patterning a substrate and materials deposited on the substrate. The substrate is typically a semiconductor wafer. The patterned features make up devices and interconnections. This process generally starts with a designer creating an integrated circuit by hierarchically defining functional components of the circuit using a hardware description language. From this high-level functional description, a physical circuit implementation dataset is created, which is usually in the form of a netlist. This netlist identifies logic cell instances from a cell library, and describes cell-to-cell connectivity.
Many phases of these electronic design activities may be performed with computer aided design (CAD) tools or electronic design automation (EDA) systems. For example, an integrated circuit designer may use a set of layout EDA application programs, such as a layout editor, to create a physical integrated circuit design layout from a logical circuit design. The layout EDA application uses geometric shapes of different materials to create the various electrical components on an integrated circuit and to represent electronic and circuit IC components as geometric objects with varying shapes and sizes. After an integrated circuit designer has created an initial integrated circuit layout, the integrated circuit designer then verifies and optimizes the integrated circuit layout using a set of EDA testing and analysis tools. Verification may include, for example, design rule checking to verify compliance with rules established for various IC parameters. The EDA layout editing tools are often performed interactively so that the designer can review and provide careful control over the details of the electronic design.
Typically, geometric information about the placement of the nodes and components onto the chip is determined by a placement process and a routing process. The placement process is a process for placing electronic components or circuit blocks on the chip and the routing process is the process for creating interconnections between the blocks and components according to the specified netlist. The task of all routers is the same—routers are given some pre-existing polygons consisting of pins on cells and optionally some pre-routes from the placers to create geometries so that all pins assigned to different nets are connected by wires and vias, that all wires and vias assigned to different nets do not overlap, and that all design rules are obeyed. That is, a router fails when two pins on the same net that should be connected are open, when two pins on two different nets that should remain open are shorted, or when some design rules are violated during routing.
A layout file is created from the placement and routing process, which assigns logic cells to physical locations in the device layout and routes their interconnections. The physical layout is typically described as many patterned layers, and the pattern of each layer is described by the union of a set of polygons. The layout data set is stored, for example in GDSII (“Graphic Data System II”) or OASIS (“Open Artwork System Interchange Standard”) formats. Component devices and interconnections of the integrated circuit are constructed layer by layer. A layer is deposited on the wafer and then it is patterned using a photolithography process and an etch process.
As the complexity and number of process steps continue to increase in modern integrated circuit manufacturing, the number of yield limiters increases tremendously. For example, there may be tens of yield limiters for an electronic circuit at the 45-nm node but thousands of yield limiters for electronic designs at the 28-nm node. As a result, the need for systematic analysis, monitoring, or sharing of data or information about defects and violations between the electronic circuit design flow and the fabrication, inspection, or testing (hereinafter “manufacturing” collectively) of the electronic circuits also increases.
Moreover, any issues discovered during manufacturing may be very costly to fix because the photomasks or even some batches of the electronic circuits have already been manufactured. In addition, manufacturing tools (e.g., metrology equipment, electronic circuit testing equipment, or fabrication equipment, etc.) may require a long time to characterize their respective recipes and to perform their intended functions (e.g., inspection, measurement, testing, etc.) and most, if not all, manufacturing tools require some threshold levels of experiences and expertise of the operator in order to fulfill their intended functions.
For example, a metrology tool operator or a testing equipment operator may not know what areas may exhibit higher risks of becoming hotspots, what areas are more critical to the electronic circuit, what areas of a die constitute fill structures, etc. As a result, the random nature of some of these manufacturing processes in focusing their processes on some areas but not others may at best identify some issues associated with the electronic circuit design and requires proportionally longer periods of time to complete as the coverage requirement grows. For example, given hundreds or even more cassettes of wafers each containing tens, hundreds, or even more dies, an engineer operating a metrology tool can only sample a few of these processed wafers (e.g., one wafer for each cassette of wafers) and only a few sites on each wafer (e.g., 24 inspection sites along the periphery with 12 additional inspection sites distributed in the remaining area of a wafer). As a result, some non-functional or dysfunctional dies are further forwarded to testing and waste resources.
The limited resolution, fidelity, or accuracy of the manufacturing tools further exacerbates the difficulties in post-tape out manufacturing processes. For example, the accuracy of modern metrology tools in pinpointing the exact location of a defect may be off by multiple wiring tracks and as much +/−450 nm in some cases. Thus, an operator operating a metrology tool may not provide sufficiently accurate information about certain failures on wafers. Rather, such manufacturing tools with limited resolution, fidelity, or accuracy may only provide information or data with limited usefulness. Consequently, even if the electronic circuit design team may forward the critical areas or critical features in a form of a text file, a spread sheet, or the like to the manufacturing equipment operators such that the operators can be made aware of such critical areas or critical features, the limited resolution, fidelity, or accuracy of the information generated by such manufacturing tools still present very limited usefulness in communicating the information back to the electronic circuit design team.
Thus, there exists a need for a method, a system, and an article of manufacture for implementing high current carrying interconnects. There also exist a need for a method, a system, and an article of manufacture for implementing high current carrying interconnects using strand routing of various topologies while satisfying various physical or electrical constraints, rules, or requirements and generating an electronic design that produces satisfactory results for various electrical analyses.